The present invention relates generally to integrated circuits (ICs), and, more particularly, to a system with a reduced number of external clock sources.
Integrated circuits usually include many circuit modules such as data converters, processors, memory arrays, and various combinational logic circuits, as well as interface circuitry. Examples of interfaces include universal serial bus (USB), double data rate (DDR), peripheral component interconnect express (PCIe), media independent interface (MII), and serial advanced technology attachment (SATA). The circuit modules exchange data using these interfaces. Thus, data and control signals are transferred among the circuit modules and interfaces within the IC. The IC requires clock signals to regulate and synchronize the flow of the data and control signals. A clock generator receives a reference clock signal from a crystal oscillator and generates multiple clock signals that are further distributed inside the IC. The characteristics of a clock generator are determined by signaling method, performance parameters, input voltage and frequency, and output voltage and frequency of the clock signals. The clock generator may use single-ended or differential signaling methods to generate the clock signals. The performance parameters of the clock generator include jitter, propagation delay, duty cycle, and output skew of the clock signals. Various circuit modules and interfaces have different clock signal requirements and hence require clock generators with different characteristics.
For example, a USB module requires a 480 megahertz (MHz) single-ended reference clock signal that is at a voltage of 1.8 volts (V) while a PCIe module requires a 5,000 MHz differential reference clock signal that is at a voltage of 1V. Thus, two separate clock generators are required. With an increase in the number of circuit modules and interfaces with various clock signal requirements, the number of clock generators increases. The multiple clock generators or clock oscillators are external to the IC, which increases the bill of materials (BOM) cost as well as require increased circuit board area. This is especially true for low cost, low performance systems. Having multiple off-chip clock generators also requires fixed clock ports on the IC. If a circuit module is placed at one side of the IC and the clock port is located at the opposite side, then the circuit modules through which the clock signal must traverse to reach its destination will introduce jitter and propagation delay in the clock signal. Thus, the overall performance of the circuit module and in turn that of the system is hampered.
Certain systems include a physical interface (PHY) chip that is placed on the circuit board (off-chip). The PHY chip includes a clock generation module that generates a clock signal that is used to synchronize the exchange of data and control signals of the IC, including memory clock signals, address and command signals, output data signals, etc. In certain cases, the clock signal requirements of the circuit modules and interfaces in the IC do not match the clock signal specifications of the clock signal generated by the PHY chip. As a result, the clock signal generated by the PHY chip may not be used.
Certain other systems include clock generators, such as PLLs that are used for clock generation. The PLLs have certain clock signal specifications. The circuit modules and interfaces that have clock signal requirements that match the clock signal specifications of the PLL are associated with the corresponding PLL. Thus, as the number of PLLs corresponding to the large number of the circuit modules and interfaces increases, the cost and area of the IC also increase.
Therefore, it would be advantageous to have a system that employs fewer clock generators, selects a location of a clock port based on a routing distance of a clock signal, uses clock signals generated by PHY chips, and reduces the BOM cost and area of the system, or otherwise addresses some or all of the above-mentioned limitations.